Do all CPUs which support AVX2 also support SSE4.2 and AVX?












6














I am planning to implement runtime detection of SIMD extensions. Is it such that if I find out that the processor has AVX2 support, it is also guaranteed to have SSE4.2 and AVX support?






sse simd avx avx2







share|improve this question



























    6














    I am planning to implement runtime detection of SIMD extensions. Is it such that if I find out that the processor has AVX2 support, it is also guaranteed to have SSE4.2 and AVX support?






    sse simd avx avx2







    share|improve this question

























      6












      6








      6







      I am planning to implement runtime detection of SIMD extensions. Is it such that if I find out that the processor has AVX2 support, it is also guaranteed to have SSE4.2 and AVX support?






      sse simd avx avx2







      share|improve this question













      I am planning to implement runtime detection of SIMD extensions. Is it such that if I find out that the processor has AVX2 support, it is also guaranteed to have SSE4.2 and AVX support?






      sse simd avx avx2




      sse simd avx avx2






      share|improve this question













      share|improve this question











      share|improve this question




      share|improve this question










      asked Nov 23 at 8:45









      Ruben

      4,7851615




      4,7851615
























          3 Answers
          3






          active

          oldest

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          4














          Support for a more-recent Intel SIMD ISA extension implies support for previous SIMD ones.



          AVX2 definitely implies AVX1.



          I think AVX1 implies all of SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2 feature bits must also be set in CPUID.



          Note that popcnt has its own feature bit, so in theory you could have a CPU with AVX2 and SSE4.2, but not popcnt.




          In theory you could make a CPU (or virtual machine) with AVX but which didn't accept the non-VEX encoding of SSE4.2 instructions like pcmpistri, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, but most software will assume that.



          But AVX1 does imply support for the VEX encoding of all SSE4.2 and earlier SIMD instructions, e.g. vpcmpistri or vminss



          gcc -mavx2 definitely implies AVX1 and previous extensions, but will only emit code that uses the VEX encoding. It will define the __SSE4_2__ macro and so on, though, so gcc does treat AVX2 as implying earlier SSE extensions and popcnt, but not AES or PCLMUL. Those are separate features even for GCC.



          (Note that MSVC doesn't have as many SIMD ISA detection macros; it has one for AVX but not for all of the earlier SSE* extensions.)




          Note that AVX512 kind of breaks the traditions. AVX512F implies support for AVX2 and everything before it, but beyond that AVX512DQ doesn't come "before" or "after" AVX512ER, for example. You can (in theory) have either, both, or neither. (In practice, Skylake-X/Cannonlake/etc. has only a bit of overlap with Xeon Phi (Knight's Landing / Knight's Mill), beyond AVX512F. https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512






          share|improve this answer





























            3














            If we set compiler option -mavx2 that GCC doesn't give an error when we use AVX or SSE intrinsics. So GCC supposes that existing of AVX2 flag is enough to run AVX and SSE code. Of course it does not garante that someone won't create CPU with AVX2 and without SSE.






            share|improve this answer





















            • I guess the question can be rephrased asking if somebody has already made a CPU (commercial) with AVX2 and without SSE.
              – Ruben
              Nov 23 at 12:59








            • 1




              @Ruben I think that creation of such CPU has no sense. When I create code with AVX2 (I have been doing this for over 5 years) I of course also use AVX and SSE code and I don't have any troubles.
              – ErmIg
              Nov 23 at 13:07





















            1














            In principle, a CPU could just support AVX2 without supporting any SSE4 instructions (Which isn't as stupid an idea as it sounds!). In practice though, if it supports AVX2, it also supports SSE4.






            share|improve this answer





















            • I'm pretty sure this is not true. AVX2 implies AVX, and AVX implies that the VEX encoding of SSE4.2 instructions like vpcmpistri are available. I think it also implies that the non-VEX encoding is available, too. In theory you could make a CPU which didn't accept the non-VEX encoding, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, though.
              – Peter Cordes
              Nov 28 at 3:58













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            3 Answers
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            3 Answers
            3






            active

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            active

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            active

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            4














            Support for a more-recent Intel SIMD ISA extension implies support for previous SIMD ones.



            AVX2 definitely implies AVX1.



            I think AVX1 implies all of SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2 feature bits must also be set in CPUID.



            Note that popcnt has its own feature bit, so in theory you could have a CPU with AVX2 and SSE4.2, but not popcnt.




            In theory you could make a CPU (or virtual machine) with AVX but which didn't accept the non-VEX encoding of SSE4.2 instructions like pcmpistri, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, but most software will assume that.



            But AVX1 does imply support for the VEX encoding of all SSE4.2 and earlier SIMD instructions, e.g. vpcmpistri or vminss



            gcc -mavx2 definitely implies AVX1 and previous extensions, but will only emit code that uses the VEX encoding. It will define the __SSE4_2__ macro and so on, though, so gcc does treat AVX2 as implying earlier SSE extensions and popcnt, but not AES or PCLMUL. Those are separate features even for GCC.



            (Note that MSVC doesn't have as many SIMD ISA detection macros; it has one for AVX but not for all of the earlier SSE* extensions.)




            Note that AVX512 kind of breaks the traditions. AVX512F implies support for AVX2 and everything before it, but beyond that AVX512DQ doesn't come "before" or "after" AVX512ER, for example. You can (in theory) have either, both, or neither. (In practice, Skylake-X/Cannonlake/etc. has only a bit of overlap with Xeon Phi (Knight's Landing / Knight's Mill), beyond AVX512F. https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512






            share|improve this answer


























              4














              Support for a more-recent Intel SIMD ISA extension implies support for previous SIMD ones.



              AVX2 definitely implies AVX1.



              I think AVX1 implies all of SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2 feature bits must also be set in CPUID.



              Note that popcnt has its own feature bit, so in theory you could have a CPU with AVX2 and SSE4.2, but not popcnt.




              In theory you could make a CPU (or virtual machine) with AVX but which didn't accept the non-VEX encoding of SSE4.2 instructions like pcmpistri, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, but most software will assume that.



              But AVX1 does imply support for the VEX encoding of all SSE4.2 and earlier SIMD instructions, e.g. vpcmpistri or vminss



              gcc -mavx2 definitely implies AVX1 and previous extensions, but will only emit code that uses the VEX encoding. It will define the __SSE4_2__ macro and so on, though, so gcc does treat AVX2 as implying earlier SSE extensions and popcnt, but not AES or PCLMUL. Those are separate features even for GCC.



              (Note that MSVC doesn't have as many SIMD ISA detection macros; it has one for AVX but not for all of the earlier SSE* extensions.)




              Note that AVX512 kind of breaks the traditions. AVX512F implies support for AVX2 and everything before it, but beyond that AVX512DQ doesn't come "before" or "after" AVX512ER, for example. You can (in theory) have either, both, or neither. (In practice, Skylake-X/Cannonlake/etc. has only a bit of overlap with Xeon Phi (Knight's Landing / Knight's Mill), beyond AVX512F. https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512






              share|improve this answer
























                4












                4








                4






                Support for a more-recent Intel SIMD ISA extension implies support for previous SIMD ones.



                AVX2 definitely implies AVX1.



                I think AVX1 implies all of SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2 feature bits must also be set in CPUID.



                Note that popcnt has its own feature bit, so in theory you could have a CPU with AVX2 and SSE4.2, but not popcnt.




                In theory you could make a CPU (or virtual machine) with AVX but which didn't accept the non-VEX encoding of SSE4.2 instructions like pcmpistri, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, but most software will assume that.



                But AVX1 does imply support for the VEX encoding of all SSE4.2 and earlier SIMD instructions, e.g. vpcmpistri or vminss



                gcc -mavx2 definitely implies AVX1 and previous extensions, but will only emit code that uses the VEX encoding. It will define the __SSE4_2__ macro and so on, though, so gcc does treat AVX2 as implying earlier SSE extensions and popcnt, but not AES or PCLMUL. Those are separate features even for GCC.



                (Note that MSVC doesn't have as many SIMD ISA detection macros; it has one for AVX but not for all of the earlier SSE* extensions.)




                Note that AVX512 kind of breaks the traditions. AVX512F implies support for AVX2 and everything before it, but beyond that AVX512DQ doesn't come "before" or "after" AVX512ER, for example. You can (in theory) have either, both, or neither. (In practice, Skylake-X/Cannonlake/etc. has only a bit of overlap with Xeon Phi (Knight's Landing / Knight's Mill), beyond AVX512F. https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512






                share|improve this answer












                Support for a more-recent Intel SIMD ISA extension implies support for previous SIMD ones.



                AVX2 definitely implies AVX1.



                I think AVX1 implies all of SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2 feature bits must also be set in CPUID.



                Note that popcnt has its own feature bit, so in theory you could have a CPU with AVX2 and SSE4.2, but not popcnt.




                In theory you could make a CPU (or virtual machine) with AVX but which didn't accept the non-VEX encoding of SSE4.2 instructions like pcmpistri, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, but most software will assume that.



                But AVX1 does imply support for the VEX encoding of all SSE4.2 and earlier SIMD instructions, e.g. vpcmpistri or vminss



                gcc -mavx2 definitely implies AVX1 and previous extensions, but will only emit code that uses the VEX encoding. It will define the __SSE4_2__ macro and so on, though, so gcc does treat AVX2 as implying earlier SSE extensions and popcnt, but not AES or PCLMUL. Those are separate features even for GCC.



                (Note that MSVC doesn't have as many SIMD ISA detection macros; it has one for AVX but not for all of the earlier SSE* extensions.)




                Note that AVX512 kind of breaks the traditions. AVX512F implies support for AVX2 and everything before it, but beyond that AVX512DQ doesn't come "before" or "after" AVX512ER, for example. You can (in theory) have either, both, or neither. (In practice, Skylake-X/Cannonlake/etc. has only a bit of overlap with Xeon Phi (Knight's Landing / Knight's Mill), beyond AVX512F. https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512







                share|improve this answer












                share|improve this answer



                share|improve this answer










                answered Nov 28 at 4:17









                Peter Cordes

                118k16180307




                118k16180307

























                    3














                    If we set compiler option -mavx2 that GCC doesn't give an error when we use AVX or SSE intrinsics. So GCC supposes that existing of AVX2 flag is enough to run AVX and SSE code. Of course it does not garante that someone won't create CPU with AVX2 and without SSE.






                    share|improve this answer





















                    • I guess the question can be rephrased asking if somebody has already made a CPU (commercial) with AVX2 and without SSE.
                      – Ruben
                      Nov 23 at 12:59








                    • 1




                      @Ruben I think that creation of such CPU has no sense. When I create code with AVX2 (I have been doing this for over 5 years) I of course also use AVX and SSE code and I don't have any troubles.
                      – ErmIg
                      Nov 23 at 13:07


















                    3














                    If we set compiler option -mavx2 that GCC doesn't give an error when we use AVX or SSE intrinsics. So GCC supposes that existing of AVX2 flag is enough to run AVX and SSE code. Of course it does not garante that someone won't create CPU with AVX2 and without SSE.






                    share|improve this answer





















                    • I guess the question can be rephrased asking if somebody has already made a CPU (commercial) with AVX2 and without SSE.
                      – Ruben
                      Nov 23 at 12:59








                    • 1




                      @Ruben I think that creation of such CPU has no sense. When I create code with AVX2 (I have been doing this for over 5 years) I of course also use AVX and SSE code and I don't have any troubles.
                      – ErmIg
                      Nov 23 at 13:07
















                    3












                    3








                    3






                    If we set compiler option -mavx2 that GCC doesn't give an error when we use AVX or SSE intrinsics. So GCC supposes that existing of AVX2 flag is enough to run AVX and SSE code. Of course it does not garante that someone won't create CPU with AVX2 and without SSE.






                    share|improve this answer












                    If we set compiler option -mavx2 that GCC doesn't give an error when we use AVX or SSE intrinsics. So GCC supposes that existing of AVX2 flag is enough to run AVX and SSE code. Of course it does not garante that someone won't create CPU with AVX2 and without SSE.







                    share|improve this answer












                    share|improve this answer



                    share|improve this answer










                    answered Nov 23 at 12:41









                    ErmIg

                    3,30212037




                    3,30212037












                    • I guess the question can be rephrased asking if somebody has already made a CPU (commercial) with AVX2 and without SSE.
                      – Ruben
                      Nov 23 at 12:59








                    • 1




                      @Ruben I think that creation of such CPU has no sense. When I create code with AVX2 (I have been doing this for over 5 years) I of course also use AVX and SSE code and I don't have any troubles.
                      – ErmIg
                      Nov 23 at 13:07




















                    • I guess the question can be rephrased asking if somebody has already made a CPU (commercial) with AVX2 and without SSE.
                      – Ruben
                      Nov 23 at 12:59








                    • 1




                      @Ruben I think that creation of such CPU has no sense. When I create code with AVX2 (I have been doing this for over 5 years) I of course also use AVX and SSE code and I don't have any troubles.
                      – ErmIg
                      Nov 23 at 13:07


















                    I guess the question can be rephrased asking if somebody has already made a CPU (commercial) with AVX2 and without SSE.
                    – Ruben
                    Nov 23 at 12:59






                    I guess the question can be rephrased asking if somebody has already made a CPU (commercial) with AVX2 and without SSE.
                    – Ruben
                    Nov 23 at 12:59






                    1




                    1




                    @Ruben I think that creation of such CPU has no sense. When I create code with AVX2 (I have been doing this for over 5 years) I of course also use AVX and SSE code and I don't have any troubles.
                    – ErmIg
                    Nov 23 at 13:07






                    @Ruben I think that creation of such CPU has no sense. When I create code with AVX2 (I have been doing this for over 5 years) I of course also use AVX and SSE code and I don't have any troubles.
                    – ErmIg
                    Nov 23 at 13:07













                    1














                    In principle, a CPU could just support AVX2 without supporting any SSE4 instructions (Which isn't as stupid an idea as it sounds!). In practice though, if it supports AVX2, it also supports SSE4.






                    share|improve this answer





















                    • I'm pretty sure this is not true. AVX2 implies AVX, and AVX implies that the VEX encoding of SSE4.2 instructions like vpcmpistri are available. I think it also implies that the non-VEX encoding is available, too. In theory you could make a CPU which didn't accept the non-VEX encoding, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, though.
                      – Peter Cordes
                      Nov 28 at 3:58


















                    1














                    In principle, a CPU could just support AVX2 without supporting any SSE4 instructions (Which isn't as stupid an idea as it sounds!). In practice though, if it supports AVX2, it also supports SSE4.






                    share|improve this answer





















                    • I'm pretty sure this is not true. AVX2 implies AVX, and AVX implies that the VEX encoding of SSE4.2 instructions like vpcmpistri are available. I think it also implies that the non-VEX encoding is available, too. In theory you could make a CPU which didn't accept the non-VEX encoding, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, though.
                      – Peter Cordes
                      Nov 28 at 3:58
















                    1












                    1








                    1






                    In principle, a CPU could just support AVX2 without supporting any SSE4 instructions (Which isn't as stupid an idea as it sounds!). In practice though, if it supports AVX2, it also supports SSE4.






                    share|improve this answer












                    In principle, a CPU could just support AVX2 without supporting any SSE4 instructions (Which isn't as stupid an idea as it sounds!). In practice though, if it supports AVX2, it also supports SSE4.







                    share|improve this answer












                    share|improve this answer



                    share|improve this answer










                    answered Nov 28 at 2:08









                    robthebloke

                    29114




                    29114












                    • I'm pretty sure this is not true. AVX2 implies AVX, and AVX implies that the VEX encoding of SSE4.2 instructions like vpcmpistri are available. I think it also implies that the non-VEX encoding is available, too. In theory you could make a CPU which didn't accept the non-VEX encoding, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, though.
                      – Peter Cordes
                      Nov 28 at 3:58




















                    • I'm pretty sure this is not true. AVX2 implies AVX, and AVX implies that the VEX encoding of SSE4.2 instructions like vpcmpistri are available. I think it also implies that the non-VEX encoding is available, too. In theory you could make a CPU which didn't accept the non-VEX encoding, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, though.
                      – Peter Cordes
                      Nov 28 at 3:58


















                    I'm pretty sure this is not true. AVX2 implies AVX, and AVX implies that the VEX encoding of SSE4.2 instructions like vpcmpistri are available. I think it also implies that the non-VEX encoding is available, too. In theory you could make a CPU which didn't accept the non-VEX encoding, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, though.
                    – Peter Cordes
                    Nov 28 at 3:58






                    I'm pretty sure this is not true. AVX2 implies AVX, and AVX implies that the VEX encoding of SSE4.2 instructions like vpcmpistri are available. I think it also implies that the non-VEX encoding is available, too. In theory you could make a CPU which didn't accept the non-VEX encoding, but I think you'd be violating Intel's guarantees about what the AVX feature bit implies. Not sure if that's formally written down in a manual, though.
                    – Peter Cordes
                    Nov 28 at 3:58




















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