How to printf or println UInt in chisel?
I am trying to execute the following code:
val num1 = 10.U
printf(p"num1 = $num1")
I am getting the following error when running this code in an example class.
[error] (run-main-8) chisel3.internal.ChiselException: Error: No implicit clock and reset.
[error] chisel3.internal.ChiselException: Error: No implicit clock and reset.
I am running the code using test:runMain <package.class>
I tried the other options in https://github.com/freechipsproject/chisel3/wiki/Printing-in-Chisel
using the printf and none of them worked.
Also tried the C style printing printf("num1 = %d",num1) and this results in the same error.
chisel
asked Nov 26 '18 at 13:26
cayluscaylus
12816
add a comment |
I am trying to execute the following code:
val num1 = 10.U
printf(p"num1 = $num1")
I am getting the following error when running this code in an example class.
[error] (run-main-8) chisel3.internal.ChiselException: Error: No implicit clock and reset.
[error] chisel3.internal.ChiselException: Error: No implicit clock and reset.
I am running the code using test:runMain <package.class>
I tried the other options in https://github.com/freechipsproject/chisel3/wiki/Printing-in-Chisel
using the printf and none of them worked.
Also tried the C style printing printf("num1 = %d",num1) and this results in the same error.
chisel
asked Nov 26 '18 at 13:26
cayluscaylus
12816
Please give more code context. Where did you wrote these two lines ? In a chisel module ?
– FabienM
Nov 26 '18 at 14:38
No this is not written in a module. Its written in the test directoryobject TestPrinting extends App { ... }Maybe this is the problem.
– caylus
Nov 26 '18 at 22:07
So seems liken the printf(p"num1 - $num1") will generate and fwrite() verilog statement, all I am trying to do here is print thing in the test bench side.
– caylus
Nov 28 '18 at 22:49
add a comment |
I am trying to execute the following code:
val num1 = 10.U
printf(p"num1 = $num1")
I am getting the following error when running this code in an example class.
[error] (run-main-8) chisel3.internal.ChiselException: Error: No implicit clock and reset.
[error] chisel3.internal.ChiselException: Error: No implicit clock and reset.
I am running the code using test:runMain <package.class>
I tried the other options in https://github.com/freechipsproject/chisel3/wiki/Printing-in-Chisel
using the printf and none of them worked.
Also tried the C style printing printf("num1 = %d",num1) and this results in the same error.
chisel
asked Nov 26 '18 at 13:26
cayluscaylus
12816
I am trying to execute the following code:
val num1 = 10.U
printf(p"num1 = $num1")
I am getting the following error when running this code in an example class.
[error] (run-main-8) chisel3.internal.ChiselException: Error: No implicit clock and reset.
[error] chisel3.internal.ChiselException: Error: No implicit clock and reset.
I am running the code using test:runMain <package.class>
I tried the other options in https://github.com/freechipsproject/chisel3/wiki/Printing-in-Chisel
using the printf and none of them worked.
Also tried the C style printing printf("num1 = %d",num1) and this results in the same error.
chisel
chisel
asked Nov 26 '18 at 13:26
cayluscaylus
12816
asked Nov 26 '18 at 13:26
cayluscaylus
12816
edited Nov 26 '18 at 13:35
caylus
asked Nov 26 '18 at 13:26
cayluscaylus
12816
asked Nov 26 '18 at 13:26
cayluscaylus
12816
asked Nov 26 '18 at 13:26
cayluscaylus
12816
12816
Please give more code context. Where did you wrote these two lines ? In a chisel module ?
– FabienM
Nov 26 '18 at 14:38
No this is not written in a module. Its written in the test directoryobject TestPrinting extends App { ... }Maybe this is the problem.
– caylus
Nov 26 '18 at 22:07
So seems liken the printf(p"num1 - $num1") will generate and fwrite() verilog statement, all I am trying to do here is print thing in the test bench side.
– caylus
Nov 28 '18 at 22:49
add a comment |
Please give more code context. Where did you wrote these two lines ? In a chisel module ?
– FabienM
Nov 26 '18 at 14:38
No this is not written in a module. Its written in the test directoryobject TestPrinting extends App { ... }Maybe this is the problem.
– caylus
Nov 26 '18 at 22:07
So seems liken the printf(p"num1 - $num1") will generate and fwrite() verilog statement, all I am trying to do here is print thing in the test bench side.
– caylus
Nov 28 '18 at 22:49
Please give more code context. Where did you wrote these two lines ? In a chisel module ?
– FabienM
Nov 26 '18 at 14:38
Please give more code context. Where did you wrote these two lines ? In a chisel module ?
– FabienM
Nov 26 '18 at 14:38
No this is not written in a module. Its written in the test directory
object TestPrinting extends App { ... } Maybe this is the problem.– caylus
Nov 26 '18 at 22:07
No this is not written in a module. Its written in the test directory
object TestPrinting extends App { ... } Maybe this is the problem.– caylus
Nov 26 '18 at 22:07
So seems liken the printf(p"num1 - $num1") will generate and fwrite() verilog statement, all I am trying to do here is print thing in the test bench side.
– caylus
Nov 28 '18 at 22:49
So seems liken the printf(p"num1 - $num1") will generate and fwrite() verilog statement, all I am trying to do here is print thing in the test bench side.
– caylus
Nov 28 '18 at 22:49
add a comment |
2 Answers
2
active
oldest
votes
The following ought to work. The withClockAndReset provides the
clock needed to trigger the printf. Its a little picky here, because withClock or withClock and a nested withReset will not work.
class Hello extends RawModule {
val io = IO(new Bundle {
val out = Output(UInt(8.W))
val myClock = Input(Clock())
val myReset = Input(Bool())
})
withClockAndReset(io.myClock, io.myReset) {
printf("out is %dn", io.out)
}
io.out := 42.U
}
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
add a comment |
There is a workaround. Printing of UInt type signals from the Chisel PeekPokeTester can be done with the help of the peek() function wrapped in a println().
println(peek(module_name.io.signal_name).toString(16))
Still have not found a way to directly print the actual signal module_name.io.signal_name the UInt type does not even have toString function so I am not sure if this can even be done.
answered Jan 8 at 19:46
cayluscaylus
12816
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
The following ought to work. The withClockAndReset provides the
clock needed to trigger the printf. Its a little picky here, because withClock or withClock and a nested withReset will not work.
class Hello extends RawModule {
val io = IO(new Bundle {
val out = Output(UInt(8.W))
val myClock = Input(Clock())
val myReset = Input(Bool())
})
withClockAndReset(io.myClock, io.myReset) {
printf("out is %dn", io.out)
}
io.out := 42.U
}
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
add a comment |
The following ought to work. The withClockAndReset provides the
clock needed to trigger the printf. Its a little picky here, because withClock or withClock and a nested withReset will not work.
class Hello extends RawModule {
val io = IO(new Bundle {
val out = Output(UInt(8.W))
val myClock = Input(Clock())
val myReset = Input(Bool())
})
withClockAndReset(io.myClock, io.myReset) {
printf("out is %dn", io.out)
}
io.out := 42.U
}
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
add a comment |
The following ought to work. The withClockAndReset provides the
clock needed to trigger the printf. Its a little picky here, because withClock or withClock and a nested withReset will not work.
class Hello extends RawModule {
val io = IO(new Bundle {
val out = Output(UInt(8.W))
val myClock = Input(Clock())
val myReset = Input(Bool())
})
withClockAndReset(io.myClock, io.myReset) {
printf("out is %dn", io.out)
}
io.out := 42.U
}
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
The following ought to work. The withClockAndReset provides the
clock needed to trigger the printf. Its a little picky here, because withClock or withClock and a nested withReset will not work.
class Hello extends RawModule {
val io = IO(new Bundle {
val out = Output(UInt(8.W))
val myClock = Input(Clock())
val myReset = Input(Bool())
})
withClockAndReset(io.myClock, io.myReset) {
printf("out is %dn", io.out)
}
io.out := 42.U
}
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
edited Nov 26 '18 at 18:33
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
answered Nov 26 '18 at 16:04
Chick MarkleyChick Markley
1,560810
1,560810
add a comment |
add a comment |
There is a workaround. Printing of UInt type signals from the Chisel PeekPokeTester can be done with the help of the peek() function wrapped in a println().
println(peek(module_name.io.signal_name).toString(16))
Still have not found a way to directly print the actual signal module_name.io.signal_name the UInt type does not even have toString function so I am not sure if this can even be done.
answered Jan 8 at 19:46
cayluscaylus
12816
add a comment |
There is a workaround. Printing of UInt type signals from the Chisel PeekPokeTester can be done with the help of the peek() function wrapped in a println().
println(peek(module_name.io.signal_name).toString(16))
Still have not found a way to directly print the actual signal module_name.io.signal_name the UInt type does not even have toString function so I am not sure if this can even be done.
answered Jan 8 at 19:46
cayluscaylus
12816
add a comment |
There is a workaround. Printing of UInt type signals from the Chisel PeekPokeTester can be done with the help of the peek() function wrapped in a println().
println(peek(module_name.io.signal_name).toString(16))
Still have not found a way to directly print the actual signal module_name.io.signal_name the UInt type does not even have toString function so I am not sure if this can even be done.
answered Jan 8 at 19:46
cayluscaylus
12816
There is a workaround. Printing of UInt type signals from the Chisel PeekPokeTester can be done with the help of the peek() function wrapped in a println().
println(peek(module_name.io.signal_name).toString(16))
Still have not found a way to directly print the actual signal module_name.io.signal_name the UInt type does not even have toString function so I am not sure if this can even be done.
answered Jan 8 at 19:46
cayluscaylus
12816
answered Jan 8 at 19:46
cayluscaylus
12816
answered Jan 8 at 19:46
cayluscaylus
12816
answered Jan 8 at 19:46
cayluscaylus
12816
12816
add a comment |
add a comment |
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Please give more code context. Where did you wrote these two lines ? In a chisel module ?
– FabienM
Nov 26 '18 at 14:38
No this is not written in a module. Its written in the test directory
object TestPrinting extends App { ... }Maybe this is the problem.– caylus
Nov 26 '18 at 22:07
So seems liken the printf(p"num1 - $num1") will generate and fwrite() verilog statement, all I am trying to do here is print thing in the test bench side.
– caylus
Nov 28 '18 at 22:49