makefile parse target to define dependencies

I have source files in several directories and I want to compile them in a one unique temporary directory, currently I use this target to create my object files :

$(BUILD_DIR)/%.o : 

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

It is working well but when I modify a source file, the object one is not recompiled. So I have to add the source file to the dependencies.

But this target doesn't work :

$(BUILD_DIR)/%.o : $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $^

Is there any way to use target name in dependencies ?

asked Nov 26 '18 at 15:07

Gautitho

465

add a comment |

I have source files in several directories and I want to compile them in a one unique temporary directory, currently I use this target to create my object files :

$(BUILD_DIR)/%.o : 

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

It is working well but when I modify a source file, the object one is not recompiled. So I have to add the source file to the dependencies.

But this target doesn't work :

$(BUILD_DIR)/%.o : $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $^

Is there any way to use target name in dependencies ?

asked Nov 26 '18 at 15:07

Gautitho

465

add a comment |

I have source files in several directories and I want to compile them in a one unique temporary directory, currently I use this target to create my object files :

$(BUILD_DIR)/%.o : 

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

It is working well but when I modify a source file, the object one is not recompiled. So I have to add the source file to the dependencies.

But this target doesn't work :

$(BUILD_DIR)/%.o : $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $^

Is there any way to use target name in dependencies ?

asked Nov 26 '18 at 15:07

Gautitho

465

I have source files in several directories and I want to compile them in a one unique temporary directory, currently I use this target to create my object files :

$(BUILD_DIR)/%.o : 

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

It is working well but when I modify a source file, the object one is not recompiled. So I have to add the source file to the dependencies.

But this target doesn't work :

$(BUILD_DIR)/%.o : $(shell echo "$(SOURCES)" | sed 's/ /n/g' | sed -nr '//$(*F).c/p')

    @echo "Compiling $@"

    $(VERBOSE) $(CC) $(CFLAGS) -c $(DEFINES) $(INCLUDES) -o $@ $^

Is there any way to use target name in dependencies ?

makefile

asked Nov 26 '18 at 15:07

Gautitho

465

asked Nov 26 '18 at 15:07

Gautitho

465

asked Nov 26 '18 at 15:07

Gautitho

465

asked Nov 26 '18 at 15:07

Gautitho

465

asked Nov 26 '18 at 15:07

Gautitho

465

add a comment |

1 Answer
1

active

oldest

votes

Assuming you are using GNU Make...

Use a pattern rule like:

obj/%.o: %.c

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

to tell make that an object file obj/<name>.o is to be compiled from a source file
<name>.c

In conjunction with this, use the VPATH special variable
to inform make of directories in which it should look for any <name>.c, if it is not
in the current directory.

Also, add an order-only prerequisite
to the pattern rule to ensure that the directory (obj) to which your object files are compiled
exists when needed:

obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

So for example, with project structure:

./

-- Makefile

-- aa/

    -- main.c

-- bb/

    -- foo.c

-- obj/ #<-- Compile object files in here

-- prog #<- program to be built

And:

Makefile

VPATH := aa:bb

SRCS := foo.c main.c

OBJS := $(addprefix obj/, $(SRCS:.c=.o))



.PHONY: all clean



all: prog



prog: $(OBJS)

    $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)



obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<



obj:

    mkdir $@



clean:

    $(RM) $(OBJS) prog

the build runs like:

$ make

cc   -c -o obj/foo.o bb/foo.c

cc   -c -o obj/main.o aa/main.c

cc  -o prog obj/foo.o obj/main.o

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

add a comment |

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1 Answer
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active

oldest

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1 Answer
1

active

oldest

votes

Assuming you are using GNU Make...

Use a pattern rule like:

obj/%.o: %.c

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

to tell make that an object file obj/<name>.o is to be compiled from a source file
<name>.c

In conjunction with this, use the VPATH special variable
to inform make of directories in which it should look for any <name>.c, if it is not
in the current directory.

Also, add an order-only prerequisite
to the pattern rule to ensure that the directory (obj) to which your object files are compiled
exists when needed:

obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

So for example, with project structure:

./

-- Makefile

-- aa/

    -- main.c

-- bb/

    -- foo.c

-- obj/ #<-- Compile object files in here

-- prog #<- program to be built

And:

Makefile

VPATH := aa:bb

SRCS := foo.c main.c

OBJS := $(addprefix obj/, $(SRCS:.c=.o))



.PHONY: all clean



all: prog



prog: $(OBJS)

    $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)



obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<



obj:

    mkdir $@



clean:

    $(RM) $(OBJS) prog

the build runs like:

$ make

cc   -c -o obj/foo.o bb/foo.c

cc   -c -o obj/main.o aa/main.c

cc  -o prog obj/foo.o obj/main.o

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

add a comment |

Assuming you are using GNU Make...

Use a pattern rule like:

obj/%.o: %.c

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

to tell make that an object file obj/<name>.o is to be compiled from a source file
<name>.c

In conjunction with this, use the VPATH special variable
to inform make of directories in which it should look for any <name>.c, if it is not
in the current directory.

Also, add an order-only prerequisite
to the pattern rule to ensure that the directory (obj) to which your object files are compiled
exists when needed:

obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

So for example, with project structure:

./

-- Makefile

-- aa/

    -- main.c

-- bb/

    -- foo.c

-- obj/ #<-- Compile object files in here

-- prog #<- program to be built

And:

Makefile

VPATH := aa:bb

SRCS := foo.c main.c

OBJS := $(addprefix obj/, $(SRCS:.c=.o))



.PHONY: all clean



all: prog



prog: $(OBJS)

    $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)



obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<



obj:

    mkdir $@



clean:

    $(RM) $(OBJS) prog

the build runs like:

$ make

cc   -c -o obj/foo.o bb/foo.c

cc   -c -o obj/main.o aa/main.c

cc  -o prog obj/foo.o obj/main.o

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

add a comment |

Assuming you are using GNU Make...

Use a pattern rule like:

obj/%.o: %.c

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

to tell make that an object file obj/<name>.o is to be compiled from a source file
<name>.c

In conjunction with this, use the VPATH special variable
to inform make of directories in which it should look for any <name>.c, if it is not
in the current directory.

Also, add an order-only prerequisite
to the pattern rule to ensure that the directory (obj) to which your object files are compiled
exists when needed:

obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

So for example, with project structure:

./

-- Makefile

-- aa/

    -- main.c

-- bb/

    -- foo.c

-- obj/ #<-- Compile object files in here

-- prog #<- program to be built

And:

Makefile

VPATH := aa:bb

SRCS := foo.c main.c

OBJS := $(addprefix obj/, $(SRCS:.c=.o))



.PHONY: all clean



all: prog



prog: $(OBJS)

    $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)



obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<



obj:

    mkdir $@



clean:

    $(RM) $(OBJS) prog

the build runs like:

$ make

cc   -c -o obj/foo.o bb/foo.c

cc   -c -o obj/main.o aa/main.c

cc  -o prog obj/foo.o obj/main.o

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

Assuming you are using GNU Make...

Use a pattern rule like:

obj/%.o: %.c

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

to tell make that an object file obj/<name>.o is to be compiled from a source file
<name>.c

In conjunction with this, use the VPATH special variable
to inform make of directories in which it should look for any <name>.c, if it is not
in the current directory.

Also, add an order-only prerequisite
to the pattern rule to ensure that the directory (obj) to which your object files are compiled
exists when needed:

obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<

So for example, with project structure:

./

-- Makefile

-- aa/

    -- main.c

-- bb/

    -- foo.c

-- obj/ #<-- Compile object files in here

-- prog #<- program to be built

And:

Makefile

VPATH := aa:bb

SRCS := foo.c main.c

OBJS := $(addprefix obj/, $(SRCS:.c=.o))



.PHONY: all clean



all: prog



prog: $(OBJS)

    $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS)



obj/%.o: %.c | obj

    $(CC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<



obj:

    mkdir $@



clean:

    $(RM) $(OBJS) prog

the build runs like:

$ make

cc   -c -o obj/foo.o bb/foo.c

cc   -c -o obj/main.o aa/main.c

cc  -o prog obj/foo.o obj/main.o

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

answered Nov 26 '18 at 15:52

Mike Kinghan

31.1k766115

add a comment |

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