VHDL Scheme simulation with demultiplexer and adder
0
I am new in VHDL and want to dive into this language for learning purposes
Scheme
Code for adder , for instance:
library ieee ;
use ieee.std_logic_1164.all;
entity add is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
pin : in STD_LOGIC;
S : out STD_LOGIC;
pi : out STD_LOGIC);
end add;
architecture gate_level of add is
begin
S <= a XOR b XOR pin ;
pi <= (a AND b) OR (pin AND a) OR (pin AND b) ;
end gate_level;
And for demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DMS is
port(d : in std_logic;
a : in std_logic_vector(2 downto 0);
q : out std_logic_vector(7 downto 0)
);
end DMS;
architecture Demultiplexer of DMS is
begin
process(d, a)
begin
if (d = '1') then
case a is
when "000" => q <= "10000000";
when "001" => q <= "01000000";
when "010" => q <= "00100000";
when "011" => q <= "00010000";
when "100" => q <= "00001000";
when "101" => q <= "00000100";
when "110" => q <= "00000010";
when "111" => q <= "00000001";
when others => q <= "00000000";
end case;
end if;
end process;
end architecture Demultiplexer;
How to connect , for instance added and demultiplexer using VHDL language?
vhdl
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
add a comment |
0
I am new in VHDL and want to dive into this language for learning purposes
Scheme
Code for adder , for instance:
library ieee ;
use ieee.std_logic_1164.all;
entity add is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
pin : in STD_LOGIC;
S : out STD_LOGIC;
pi : out STD_LOGIC);
end add;
architecture gate_level of add is
begin
S <= a XOR b XOR pin ;
pi <= (a AND b) OR (pin AND a) OR (pin AND b) ;
end gate_level;
And for demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DMS is
port(d : in std_logic;
a : in std_logic_vector(2 downto 0);
q : out std_logic_vector(7 downto 0)
);
end DMS;
architecture Demultiplexer of DMS is
begin
process(d, a)
begin
if (d = '1') then
case a is
when "000" => q <= "10000000";
when "001" => q <= "01000000";
when "010" => q <= "00100000";
when "011" => q <= "00010000";
when "100" => q <= "00001000";
when "101" => q <= "00000100";
when "110" => q <= "00000010";
when "111" => q <= "00000001";
when others => q <= "00000000";
end case;
end if;
end process;
end architecture Demultiplexer;
How to connect , for instance added and demultiplexer using VHDL language?
vhdl
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
You need to create another entity and instantiate both the DMS and add entities, and connect them together with signals.
– Tricky
Nov 29 '18 at 7:34
add a comment |
0
0
0
I am new in VHDL and want to dive into this language for learning purposes
Scheme
Code for adder , for instance:
library ieee ;
use ieee.std_logic_1164.all;
entity add is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
pin : in STD_LOGIC;
S : out STD_LOGIC;
pi : out STD_LOGIC);
end add;
architecture gate_level of add is
begin
S <= a XOR b XOR pin ;
pi <= (a AND b) OR (pin AND a) OR (pin AND b) ;
end gate_level;
And for demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DMS is
port(d : in std_logic;
a : in std_logic_vector(2 downto 0);
q : out std_logic_vector(7 downto 0)
);
end DMS;
architecture Demultiplexer of DMS is
begin
process(d, a)
begin
if (d = '1') then
case a is
when "000" => q <= "10000000";
when "001" => q <= "01000000";
when "010" => q <= "00100000";
when "011" => q <= "00010000";
when "100" => q <= "00001000";
when "101" => q <= "00000100";
when "110" => q <= "00000010";
when "111" => q <= "00000001";
when others => q <= "00000000";
end case;
end if;
end process;
end architecture Demultiplexer;
How to connect , for instance added and demultiplexer using VHDL language?
vhdl
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
I am new in VHDL and want to dive into this language for learning purposes
Scheme
Code for adder , for instance:
library ieee ;
use ieee.std_logic_1164.all;
entity add is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
pin : in STD_LOGIC;
S : out STD_LOGIC;
pi : out STD_LOGIC);
end add;
architecture gate_level of add is
begin
S <= a XOR b XOR pin ;
pi <= (a AND b) OR (pin AND a) OR (pin AND b) ;
end gate_level;
And for demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DMS is
port(d : in std_logic;
a : in std_logic_vector(2 downto 0);
q : out std_logic_vector(7 downto 0)
);
end DMS;
architecture Demultiplexer of DMS is
begin
process(d, a)
begin
if (d = '1') then
case a is
when "000" => q <= "10000000";
when "001" => q <= "01000000";
when "010" => q <= "00100000";
when "011" => q <= "00010000";
when "100" => q <= "00001000";
when "101" => q <= "00000100";
when "110" => q <= "00000010";
when "111" => q <= "00000001";
when others => q <= "00000000";
end case;
end if;
end process;
end architecture Demultiplexer;
How to connect , for instance added and demultiplexer using VHDL language?
vhdl
vhdl
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
asked Nov 28 '18 at 21:00
Andrew StriletskyiAndrew Striletskyi
61
61
You need to create another entity and instantiate both the DMS and add entities, and connect them together with signals.
– Tricky
Nov 29 '18 at 7:34
add a comment |
You need to create another entity and instantiate both the DMS and add entities, and connect them together with signals.
– Tricky
Nov 29 '18 at 7:34
You need to create another entity and instantiate both the DMS and add entities, and connect them together with signals.
– Tricky
Nov 29 '18 at 7:34
You need to create another entity and instantiate both the DMS and add entities, and connect them together with signals.
– Tricky
Nov 29 '18 at 7:34
add a comment |
0
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You need to create another entity and instantiate both the DMS and add entities, and connect them together with signals.
– Tricky
Nov 29 '18 at 7:34